PCIe on KnightLi Blog

What is Above 4G Decoding? Why multi-PCIe systems, NAS expansion cards, and large-VRAM GPUs should enable it

Sun, 24 May 2026 00:51:13 +0800

Above 4G Decoding is a low-level PCIe resource allocation option in the motherboard BIOS. It often appears when troubleshooting NAS boxes, mini PCs, workstations, multi-GPU systems, routers, HBA / SATA expansion cards, and local AI machines.

In simple terms, it allows a 64-bit system to assign PCIe devices’ MMIO address space above the 4GB physical address range.

That sounds low-level, but the problem is very real: when a motherboard has a GPU, NVMe drive, NIC, SATA expansion card, capture card, HBA, and other PCIe devices, forcing all of them to compete for address space below 4GB can cause resource allocation failures, missing devices, or even boot freezes.

Why is there a 4GB boundary?

The 4GB boundary is a historical legacy of the 32-bit era.

A 32-bit address space can address at most:

`1`	`2^32 bytes = 4GB`

Modern computers have 64-bit CPUs and operating systems, and memory sizes of 16GB, 32GB, 64GB, or more are common. But during POST and PCIe device initialization, motherboards still need to account for old compatibility assumptions. Many PCIe device resource mappings are initially arranged below the 4GB address boundary.

The problem is that the space below 4GB is not only for RAM. The system must reserve part of it for hardware devices.

That is where MMIO comes in.

What is MMIO?

MMIO means Memory-Mapped I/O.

The CPU cannot directly touch the internal registers or memory windows of PCIe devices as if they were normal RAM. Instead, part of the device’s registers, buffers, or VRAM window is mapped into the system address space. When the CPU reads or writes that address range, it is effectively communicating with the PCIe device.

Roughly:

A device needs an address range.
The motherboard assigns a physical system address range to it.
When the CPU accesses that address range, it actually accesses the PCIe device.

This mapped region is not ordinary RAM. It is an address window occupied by hardware.

In old default configurations, many devices’ MMIO regions are constrained below 4GB, often around the 3GB to 4GB area. This usually works with few devices, but becomes crowded as more devices are installed.

What is BAR?

Every PCIe device uses BAR to tell the motherboard how much address space it needs.

BAR means Base Address Register. Its job is to say:

`1`	`I need a block of MMIO space. Please assign me an address range.`

GPUs, NVMe drives, SATA controllers, NICs, HBAs, and USB expansion cards may all need BAR space. More devices means more address windows. GPUs may need especially large mappings.

If the available MMIO space below 4GB is insufficient, the motherboard may fail to allocate resources to later devices.

What happens if Above 4G Decoding is disabled?

When Above 4G Decoding is disabled, the motherboard tends to pack PCIe resources below the 4GB boundary. With only a few devices, you may not notice anything. With many devices, problems can appear.

Common setups include:

A discrete GPU.
One or more NVMe SSDs.
A JMB585 / ASM1166 SATA expansion card.
A 2.5G / 10G NIC.
A Wi-Fi / Bluetooth module.
Extra HBAs, capture cards, or USB expansion cards.

All of these devices request BAR / MMIO address space from the motherboard. If the below-4GB region is full, the motherboard may show:

A PCIe card is not recognized.
The device does not appear in BIOS.
Linux / Windows reports missing devices or resource errors.
Boot freezes during POST.
Black screen or blinking cursor.
Each card works alone, but the system fails when multiple cards are installed together.

In JMB585 SATA expansion card scenarios, users often see the motherboard hang before BIOS, or the expansion card disappear after adding NVMe or NIC devices. Besides Option ROM, CSM, and PCIe Gen speed, PCIe address-space allocation is also worth checking.

What changes when Above 4G Decoding is enabled?

Enable:

`1`	`Above 4G Decoding = Enabled`

This tells the motherboard that PCIe devices supporting 64-bit addressing may have their MMIO resources allocated above 4GB.

Then PCIe devices no longer need to fight for the small below-4GB region. The motherboard can place some BAR / MMIO mappings at higher addresses, reducing resource conflicts.

For modern 64-bit systems, this is usually a reasonable setting, especially on:

Multi-disk NAS machines.
Multi-NIC routers.
Mini PCs with SATA / HBA expansion cards.
Multi-GPU workstations.
AI inference or training machines.
Desktop systems with GPU, NVMe, capture cards, and expansion cards.

Its goal is not to improve normal application performance. Its goal is to make hardware resource allocation less cramped.

Relationship with JMB585 / SATA expansion cards

A JMB585-style SATA expansion card may not need huge MMIO space by itself. The problem is often not how much this card needs alone, but how all PCIe devices in the system compete for address space together.

For example, a mini PC may include:

An NVMe system disk.
An onboard NIC.
A Wi-Fi module.
A JMB585 five-port SATA expansion card.
Possibly a discrete GPU or other controller.

If BIOS resource allocation is conservative, JMB585 may be one of the last devices initialized. Earlier devices have already consumed much of the below-4GB space. When JMB585 asks for BAR space, the motherboard may fail or enter an abnormal state.

Enabling Above 4G Decoding lets the motherboard place some device resources above 4GB, reducing the chance of conflict.

It cannot repair a bad card or solve every PCIe link-training problem, but it is well worth trying when issues appear only after several devices are installed.

Relationship with Resizable BAR / SAM

Many users first notice Above 4G Decoding when configuring GPU performance features, such as:

Resizable BAR
Re-Size BAR
ReBAR
Smart Access Memory
SAM

They are related, but not the same thing.

Above 4G Decoding is the foundation. It allows PCIe device MMIO resources to be assigned above 4GB.

Resizable BAR is a further capability. Traditionally, even if the CPU can access GPU memory, it often does so through a relatively small window, such as a 256MB mapping. With ReBAR, the CPU can map a larger portion of the GPU’s VRAM at once, theoretically reducing access switching overhead.

Many motherboards require Above 4G Decoding to be enabled before Resizable BAR can be enabled. So:

Above 4G Decoding: allows device addresses above 4GB.
Resizable BAR / SAM: allows the GPU BAR window to become larger.

For NAS and SATA expansion cards, the important part is usually the PCIe address space provided by the first option, not ReBAR itself.

Side effects

On modern 64-bit Windows, Linux, Ubuntu, Debian, TrueNAS, Proxmox, and similar systems, enabling Above 4G Decoding usually has no obvious downside.

Still, keep these points in mind:

Very old 32-bit operating systems may not be suitable.
Some very old BIOS implementations or legacy PCIe devices may be incompatible.
If the system cannot boot after changing BIOS settings, clear CMOS or restore defaults.
If you enable ReBAR / SAM as well, verify that the GPU, motherboard, OS, and driver support it.

On modern hardware and 64-bit systems, it is usually a healthy low-level setting to keep enabled, especially when multiple PCIe devices are installed.

When should you enable it?

Consider enabling Above 4G Decoding when:

You use a 64-bit operating system.
Multiple PCIe devices are installed.
You have a discrete GPU, especially with 4GB or more VRAM.
You use JMB585, ASM1166, HBA, RAID, capture, or other expansion cards.
You are building a multi-disk NAS or router.
You use multi-GPU, AI accelerator, or local LLM hardware.
Installing a PCIe card causes boot freeze, black screen, or blinking cursor.
Each device works alone, but combinations fail.

If you are troubleshooting a JMB585 SATA expansion card freezing during POST, check it together with:

Disable CSM.
Disable unnecessary Storage OpROM.
Change PCIe speed from Auto or Gen3 to Gen2.
Enable Above 4G Decoding.
Try another PCIe slot.

What is it called in BIOS?

Different motherboard vendors use slightly different names. Common names include:

Above 4G Decoding
Above 4GB MMIO BIOS assignment
Memory Mapped I/O above 4GB
64-bit PCIe decoding
PCI 64-bit Resource Handling

Common menu locations include:

Advanced
PCIe Settings
PCI Subsystem Settings
Chipset
North Bridge
IO Ports
Boot

Some motherboards place it near Resizable BAR, while others hide it under advanced PCIe or chipset settings.

Summary

The core purpose of Above 4G Decoding is to let the motherboard allocate PCIe device MMIO / BAR address space above 4GB. It does not fix drivers; it addresses BIOS / PCIe resource allocation.

On a simple PC with few devices, it may feel invisible. On a multi-disk NAS, multi-NIC router, mini PC with JMB585 / ASM1166 SATA expansion card, multi-GPU workstation, or local AI box, it matters.

If installing a PCIe expansion card causes BIOS freezes, black screens, blinking cursor, missing devices, or failure only when multiple devices are installed together, Above 4G Decoding = Enabled is a BIOS option worth checking early. It is not a cure-all, but it helps modern 64-bit hardware escape the old below-4GB address-space limitation and reduces PCIe resource conflicts.

PCIe expansion card causes a blinking cursor before BIOS: how to troubleshoot POST freezes

Sun, 24 May 2026 00:46:52 +0800

If a PCIe expansion card is installed and the machine cannot even reach the BIOS screen, stopping at a black screen or blinking cursor before the motherboard finishes booting, this is usually not a Linux driver issue. It is an earlier hardware-level freeze.

At this stage, the operating system has not loaded yet, so Linux kernel parameters such as pci=nomsi and pcie_aspm=off cannot help. The problem happens during POST, the power-on self-test stage. Common failure points include PCIe link training, PCIe resource allocation, Option ROM loading, Legacy / UEFI compatibility conflicts, or a faulty expansion card.

In short: if you cannot even enter BIOS, do not start by changing Linux. First make the motherboard complete POST.

What this failure means

During a normal boot, the motherboard scans PCIe devices, assigns bus, I/O, MMIO, and other resources, and decides whether to load any Option ROM provided by the device. Some SATA expansion cards, HBAs, NICs, capture cards, or adapters include firmware for boot support or device initialization, and the motherboard firmware may try to read it.

If the expansion card, motherboard BIOS, PCIe slot, power, attached device, or Option ROM is incompatible, the system may freeze during motherboard self-test. Typical symptoms include:

Black screen with only a blinking cursor.
Stuck before or after the motherboard logo.
Del, F2, F11, or F12 cannot enter BIOS or the boot menu.
Everything works after removing the PCIe expansion card.
NVMe, GPU, NIC, or existing boot device works normally when the card is removed.

This means the motherboard has not had a chance to hand control to the operating system; the card has already blocked the boot process.

Which PCIe expansion cards commonly trigger this

This POST freeze does not only happen with JMB585 SATA cards. Any PCIe device that the motherboard needs to initialize, allocate resources for, or load Option ROM from can trigger similar problems.

Common examples include:

JMB585, ASM1166, and similar PCIe SATA expansion cards.
LSI / Broadcom HBA or RAID cards.
2.5G, 10G, copper, or fiber NICs.
PCIe to M.2 / U.2 / SATA adapters.
Video capture cards.
USB 3.x expansion cards.
Older GPUs, RAID cards, or server pull cards with Option ROM.
Cheap PCIe cards with poor build quality, modified firmware, or broken EEPROM.

The device may not be “dead.” It may simply be incompatible with the current motherboard BIOS, PCIe lane routing, PCIe speed, boot mode, or address resource allocation.

Why Linux kernel parameters do not work yet

Parameters such as pci=nomsi, pcie_aspm=off, and libata.force are Linux kernel boot parameters. They only take effect after the kernel has loaded.

A blinking cursor before BIOS, a freeze before the motherboard logo, or a keyboard that cannot enter BIOS means the system is still in POST. The code running is motherboard firmware, not the Linux kernel. Linux has not started yet, so it cannot read those parameters.

For this class of failure, do not start by editing /etc/default/grub. Focus first on:

BIOS / UEFI boot mode.
CSM / Legacy compatibility layer.
PCIe Option ROM.
PCIe link training.
PCIe address space and resource allocation.
Expansion card, slot, power, and attached devices.

Step 1: disconnect devices attached to the expansion card

Start with the lowest-risk test. Leave the PCIe expansion card installed, but disconnect SATA data cables, attached device cables, or disk power from whatever is connected to it. Let the card sit in the motherboard with no attached devices.

Then boot and test:

If the system can enter BIOS after disconnecting disks or devices, the expansion card itself probably did not hard-lock the motherboard. The problem may be one disk, cable, power path, or boot-device detection.
If it still freezes, the problem is more likely between the expansion card and the motherboard PCIe / BIOS compatibility.

Why can attached disks cause POST freezes? Common reasons include:

A disk has a damaged boot sector or partition table, and the BIOS misidentifies it as a boot device and hangs while reading it.
Multiple HDDs spin up at once and the power supply cannot handle the transient current.
A SATA cable has poor contact, causing controller initialization to time out.
A disk is in poor health and slows down initialization.

If it boots after disconnecting disks, reconnect them one by one to find the specific disk or cable that triggers the problem.

Step 2: remove the card and disable CSM in BIOS

Many PCIe expansion cards freeze during POST because of the CSM / Legacy boot compatibility layer.

CSM stands for Compatibility Support Module. It lets UEFI motherboards support old Legacy boot behavior. The problem is that some cheap SATA expansion cards or modified cards include old Option ROMs. When the motherboard runs in CSM mode, it may try to load those old boot firmwares, which can conflict with modern UEFI firmware.

Why CSM and Option ROM can freeze POST

During POST, the motherboard enumerates PCIe devices and checks whether they provide boot firmware. Older storage cards, RAID cards, HBAs, NICs, and SATA expansion cards may provide Option ROM so the motherboard can recognize the device before the operating system starts, or even boot from it.

The problem is that Option ROM depends heavily on BIOS implementation. Some expansion cards have outdated, modified, damaged, or server-specific Option ROMs. When a modern consumer motherboard tries to load them under CSM / Legacy mode, it may enter an initialization loop, black screen, blinking cursor, or keyboard lock.

Disabling CSM and Storage OpROM prevents the motherboard from executing the card’s own pre-boot firmware. If your system disk is not connected to that expansion card, most NAS and data-disk scenarios do not need to boot from it. Letting Linux or Windows recognize it after boot is usually more stable.

Steps:

Shut down and remove power, then remove the PCIe expansion card.
Boot with the original GPU, iGPU, or existing boot device and enter BIOS.
Find CSM, Compatibility Support Module, or Legacy Boot.
Set CSM to Disabled.
Use UEFI Only boot mode if possible.
Save BIOS settings and shut down.
Reinstall the PCIe expansion card and test again.

If disabling CSM lets the machine pass POST, the likely cause was Legacy Option ROM or boot compatibility conflict.

Step 3: disable PCIe / Storage Option ROM

Some BIOS menus provide more detailed Option ROM controls, such as:

PCIe Option ROM
Storage OpROM
Mass Storage Controller Option ROM
Launch Storage OpROM Policy
Option ROM Messages

If you find a similar option, set the expansion card slot or storage-controller Option ROM to:

`1`	`Disabled`

or:

`1`	`Do Not Launch`

This tells the motherboard not to load boot firmware from the card, and to leave it as an ordinary PCIe device for the operating system to detect later.

If the system disk is not attached to this expansion card and the card is only used for data disks, NAS disks, warehouse disks, NICs, or capture devices, you usually do not need to boot from it. Disabling its Option ROM is often safer.

Step 4: force PCIe speed to Gen2 or Gen1

Many cards advertise PCIe Gen3 links, but the motherboard, adapter, cabling, slot, or card build quality may not be good enough. PCIe link training may fail at Gen3 speed, leaving the motherboard waiting for device initialization.

What PCIe Gen3 link-training failure looks like

When a PCIe device is installed, the motherboard and device negotiate link width and speed, such as x1, x2, x4, and Gen1, Gen2, Gen3. This process is called Link Training.

If the device, slot, adapter, motherboard traces, or power is unstable, both sides may fail to negotiate at higher speeds. Common symptoms include:

Black screen or blinking cursor before BIOS after installing the card.
Motherboard logo hangs for a long time and keyboard input does not respond.
Sometimes it boots, sometimes it hard-freezes.
Forcing PCIe Gen2 makes it stable.
Moving to another slot makes it stable.
The card works in a chipset slot but not a CPU-connected slot, or the opposite.

This is not an operating-system disk-drop issue. The motherboard and device have not finished PCIe link initialization yet. Forcing Gen2 / Gen1 lowers signal rate and trades theoretical bandwidth for stable boot.

Steps:

Remove the PCIe expansion card.
Enter BIOS.
Find the speed setting for the target PCIe slot, such as PCIe Speed, PCIe Link Speed, or Max Link Speed.
Change Auto or Gen3 to Gen2.
If Gen2 is still unstable, try Gen1.
Save, shut down, reinstall the card, and test.

For SATA HDDs, Gen2 x1 or Gen2 x2 is often enough. When stability matters, do not insist on Gen3.

If BIOS does not provide a PCIe speed setting, only then consider physical down-training methods. Some users tape selected gold-finger pins to force a card into x1 mode and test whether the second PCIe lane or high-speed signal quality is the problem. This is risky and easy to do wrong, so it should not be the first choice. Prefer BIOS speed limiting.

Step 5: enable Above 4G Decoding

If the motherboard has NVMe, GPU, wireless card, HBA, capture card, or multiple PCIe devices, BIOS must assign address space and MMIO resources during POST. Older boards or conservative BIOS resource allocation may freeze because of insufficient resources or address conflicts.

Try enabling:

`1`	`Above 4G Decoding`

It is often under Advanced, PCIe Settings, PCI Subsystem Settings, Chipset, or similar menus.

This option allows PCIe devices to use address space above 4GB, helping reduce resource allocation problems in multi-device systems. Although it is often mentioned for GPU passthrough, mining cards, HBAs, and multi-PCIe setups, it is also worth trying for SATA expansion cards that freeze during POST.

Step 6: change PCIe slots

Do not test only one slot. Different PCIe slots may be wired differently:

The long slot near the CPU is often CPU-connected and intended for GPUs.
Some short slots or secondary long slots may come from the chipset PCH.
Some slots share lanes with NVMe, SATA, Wi-Fi, or other devices.

If the expansion card freezes in a CPU-connected slot, try a chipset slot or lower-bandwidth slot. If the PCH slot is unstable, try another slot.

Also check the motherboard manual for lane-sharing rules, such as “this PCIe slot is disabled when this M.2 slot is populated.”

Recommended fast troubleshooting path

If you want to restore boot quickly, try this order:

Disconnect all devices attached to the expansion card, such as SATA disks, U.2 disks, or external cables.
If it still freezes, remove the card and enter BIOS.
Disable CSM and switch to UEFI Only.
Disable Storage OpROM or related PCIe Option ROM.
Enable Above 4G Decoding.
Force the target PCIe slot to Gen2; if that fails, try Gen1.
Save, shut down, reinstall the PCIe expansion card, and test.
If it passes POST, reconnect disks or devices one by one.

This path prioritizes the two most common causes: Legacy / Option ROM conflicts and PCIe Gen3 link-training incompatibility.

How to tell whether the card is bad or the motherboard is incompatible

If all steps above still end with a blinking cursor, do two cross-checks:

Test the same expansion card in another computer.
Test a known-good similar PCIe expansion card in the current motherboard.

Use this logic:

The same card freezes multiple computers: the card likely has a hardware or firmware problem.
The card freezes only on this motherboard but works elsewhere: motherboard BIOS, slot wiring, PCIe speed, or resource allocation is more likely.
Other similar expansion cards work in this motherboard: the original card is more suspicious.
Other PCIe devices are also unstable in this motherboard: suspect the slot, power, BIOS settings, or PCIe lane sharing.

If this card freezes multiple computers while other cards work on the current board, possible causes include:

Damaged expansion-card EEPROM / Option ROM data.
Short circuit or power problem on the card.
Gold-finger, solder joint, crystal, or power-chip hardware issue.
Firmware incompatible with many motherboard BIOS implementations.

If it freezes only on one motherboard, suspect BIOS, slot lanes, PCIe speed, CSM, or resource allocation.

Do not treat OS parameters as BIOS-stage fixes

Again, if the machine has not entered Linux, kernel parameters such as pci=nomsi, pcie_aspm=off, and libata.force do not take effect.

They only handle problems after the operating system takes over the hardware, such as disk drops, interrupt errors, and PCIe ASPM wake failures under Linux. They cannot help with a blinking cursor before BIOS or a POST-stage freeze because they never get a chance to run.

For this class of failure, focus on:

BIOS settings.
PCIe link training.
Option ROM.
Slot and resource allocation.
Physical condition of the expansion card and attached devices.

Summary

When a PCIe expansion card causes a blinking cursor before BIOS, the system is stuck during POST. The most common fixes are:

Disconnect all attached devices to rule out disk or power triggers.
Disable CSM and use pure UEFI.
Disable Storage / PCIe Option ROM.
Lower PCIe speed from Auto / Gen3 to Gen2 or Gen1.
Enable Above 4G Decoding.
Try another PCIe slot.

If none of these works and the card also freezes other computers, strongly suspect hardware or firmware damage on the card itself. For NAS and storage servers, stability matters more than attractive specs. With POST-level freezes, first make the motherboard pass self-test reliably, then troubleshoot Linux kernel parameters and drivers.

pci=nomsi and pcie_aspm=off explained: troubleshooting SATA expansion cards not detected, dropping disks, or freezing on Linux

Sun, 24 May 2026 00:41:23 +0800

When using PCIe SATA expansion cards on Linux or Ubuntu, users often run into disks not being detected, disks dropping after some runtime, system freezes, or boot problems around PCIe link training. Common examples include JMB585 and ASM1166 SATA cards, especially in NAS boxes, mini PCs, industrial PCs, modified motherboards, or cheap adapter setups.

pci=nomsi and pcie_aspm=off are two Linux kernel parameters often used when troubleshooting this class of problem. They both involve PCIe, but they address different layers:

pci=nomsi mainly targets interrupt signaling problems, meaning the way the device notifies the CPU is unreliable.
pcie_aspm=off mainly targets PCIe power management problems, meaning the link fails to wake reliably after entering a low-power state.

If you treat these two options as the same kind of fix, troubleshooting becomes guesswork. A better approach is to look at the symptoms and decide whether interrupts, link power management, or the hardware itself is the more likely suspect.

pci=nomsi: disable message-signaled interrupts

pci=nomsi can be read as:

PCI: PCI-related devices.
no: disable.
MSI: Message Signaled Interrupts.

It tells the Linux kernel not to use MSI / MSI-X interrupt mechanisms for PCI devices, and to fall back to the older INTx interrupt mode.

What is MSI?

Traditionally, hardware devices notify the CPU through physical interrupt pins, known as legacy IRQs. This works, but sharing and scaling are limited.

MSI / MSI-X came later. Instead of pulling a physical interrupt pin, the device writes a message to a specific memory address. When the CPU receives that message, it knows which device raised the interrupt. On modern systems, MSI / MSI-X is usually more flexible and better suited for high-concurrency devices.

The problem is that not every PCIe expansion card implements MSI reliably. Some cheap cards, retired enterprise cards, bridge-chip designs, or SATA controllers with poor firmware may produce abnormal MSI messages, lost interrupts, or interrupt storms under Linux drivers.

Common symptoms include:

The machine hangs while detecting the PCIe expansion card during boot.
The SATA expansion card does not detect disks at all.
Random system freezes.
dmesg shows errors such as irq xx: nobody cared.
The card appears to work under Windows but is unstable under Linux.

The core problem is not the hard disk or filesystem. It is the interrupt communication path between the device and CPU.

What happens after adding pci=nomsi?

Enable:

`1`	`pci=nomsi`

This tells the Linux kernel not to let PCI devices use advanced MSI message interrupts, and to fall back to legacy INTx interrupts.

This may slightly reduce performance and interrupt handling efficiency, especially on high-throughput or high-interrupt devices. For home NAS setups, SATA expansion cards, and ordinary hard-drive arrays, the practical impact is usually small. The value is that it bypasses MSI compatibility bugs in some device firmware or bridge chips, allowing the system to identify the device and handle I/O reliably.

In short, pci=nomsi addresses “the device’s way of notifying the CPU is unreliable.”

pcie_aspm=off: disable PCIe Active State Power Management

pcie_aspm=off can be read as:

PCIe: PCI Express.
ASPM: Active State Power Management.
off: disable.

It disables PCIe link power-saving mechanisms, preventing PCIe links from entering low-power states.

What is ASPM?

ASPM is a PCIe power-saving mechanism. When the system sees that a PCIe link is idle, it can move the link into a lower-power state such as L0s or L1. When the device needs to transfer data again, the link wakes back up to normal operation.

On well-designed hardware, this saves power and is almost invisible to users. On some consumer motherboards, mini PCs, industrial systems, cheap SATA cards, adapters, or systems with weaker signal quality, the problem is “it goes to sleep and does not wake cleanly.”

A typical case is a JMB585 or ASM1166 PCIe SATA card entering a low-power state after being idle. The next disk access requires the link to wake from L1. If the controller, motherboard, riser, power, or firmware quality is not good enough, wake-up may be too slow or the physical signal may glitch. The Linux kernel may then think the device briefly disappeared.

Typical dmesg messages include:

1
2
3

pcieport 0000:00:1c.0: PCIe Bus Error: severity=Corrected, type=Physical Layer
ata1: link is slow to respond, please be patient
ata1: COMRESET failed (errno=-16)

This may be followed by:

Disk dropout.
Degraded arrays.
Filesystem remounted read-only.
NAS services failing.
System I/O hangs.
Disk temporarily returns after reboot.

The frustrating part is that the problem may not appear at boot. It often happens after the system has been running, after an idle period, or during a load transition.

What happens after adding pcie_aspm=off?

Enable:

`1`	`pcie_aspm=off`

This tells the kernel to disable system-wide PCIe ASPM. PCIe links should remain in normal connected states as much as possible, whether idle or busy, instead of entering low-power sleep.

The side effect is slightly higher power use. For desktops, NAS boxes, and mini PCs, this is often only hundreds of milliwatts to one or two watts. For laptops, it may affect battery life. The benefit is fewer disk drops, link-training errors, and physical-layer errors caused by PCIe link sleep and wake.

In short, pcie_aspm=off addresses “the PCIe link does not wake reliably after sleeping.”

The difference between the two parameters

They solve two different classes of problems:

Parameter	Core problem	Common symptoms	Main side effect
`pci=nomsi`	Interrupt signaling conflicts, poor MSI / MSI-X compatibility	Boot hangs, no disk detection, `irq xx: nobody cared`, system freeze	Slightly lower interrupt efficiency under very high concurrency
`pcie_aspm=off`	PCIe power-save wake failure, unstable link signal	Works at boot, drops disks later, `PCIe Bus Error`, `COMRESET failed`	Slightly higher power use, slightly lower laptop battery life

They do not replace each other. One controls interrupts, the other controls link power management.

If the system hangs during boot or the device is never detected, suspect pci=nomsi first. If it boots normally but drops disks later, or dmesg shows Physical Layer, COMRESET, or “link is slow to respond” messages, suspect pcie_aspm=off first.

Should you add both?

Many NAS users add both at once:

`1`	`pci=nomsi pcie_aspm=off`

This is a quick troubleshooting method, especially with JMB585, ASM1166, mini PCs, adapter cards, uncertain power, and uncertain cabling. It can bypass MSI compatibility issues and ASPM wake problems at the same time.

From a troubleshooting perspective, it is better to record symptoms and logs first:

If you see interrupt errors or boot hangs, try pci=nomsi first.
If you see disk drops, PCIe Bus Error, or COMRESET after runtime, try pcie_aspm=off first.
If the system is unstable and you need to restore service quickly, add both, then test them separately later.

This helps you identify the actual class of problem, which is useful when changing cards, slots, motherboards, or BIOS settings later.

How to make it permanent on Ubuntu / Debian

Edit the Grub configuration file:

`1`	`sudo nano /etc/default/grub`

Find this line:

`1`	`GRUB_CMDLINE_LINUX_DEFAULT="quiet splash"`

Append the parameters inside the quotes, separated by spaces. For example:

`1`	`GRUB_CMDLINE_LINUX_DEFAULT="quiet splash pci=nomsi pcie_aspm=off"`

Save and exit. In Nano, press Ctrl+O, confirm with Enter, then press Ctrl+X.

Update Grub and reboot:

1
2

sudo update-grub
sudo reboot

After reboot, check whether the kernel command line is active:

`1`	`cat /proc/cmdline`

If the output contains pci=nomsi and pcie_aspm=off, the parameters are active for the current boot.

What else should you check?

These two parameters are useful, but they are not universal fixes for every disk-drop problem. When troubleshooting SATA expansion cards and NAS disk drops, also check:

Loose or poor-quality SATA data cables.
Stable disk power, especially when many disks spin up at once.
Poor PCIe slot contact.
Expansion card overheating.
BIOS options related to PCIe ASPM, Above 4G Decoding, and PCIe speed.
Known firmware issues in the SATA expansion card.
Disk SMART warnings, bad sectors, or I/O errors in system logs.

If disk SMART is already reporting errors, or power delivery is unstable, kernel parameters alone will not solve the underlying problem.

Summary

pci=nomsi and pcie_aspm=off are both common troubleshooting parameters for unstable PCIe SATA expansion cards on Linux, but they work at different layers:

pci=nomsi: disables MSI / MSI-X to bypass interrupt compatibility issues.
pcie_aspm=off: disables PCIe ASPM to avoid wake failures after link power saving.

For JMB585, ASM1166, NAS systems, mini PCs, and cheap PCIe cards, these two parameters often help. The safer approach is to inspect dmesg, decide whether the problem looks like interrupts or link power management, then choose one or both.

They are troubleshooting tools, not a replacement for good hardware. If the system becomes stable after adding them, the problem is likely in interrupt compatibility or PCIe power management. If disks still drop, continue checking power, cables, cooling, disk health, and the expansion card itself.

TerraMaster F2-221 NAS Backplane Pinout Notes

Mon, 04 May 2026 06:02:56 +0800

This note documents the non-standard backplane connector pinout of the TerraMaster F2-221 NAS. The connector looks close to a PCIe edge connector, but it is not a standard PCIe slot. It is a custom TerraMaster backplane interface.

The connector carries SATA, power, reset, and PCIe signals at the same time. Once PCIe1 x1 is confirmed usable, a custom backplane can expose an M.2 M-key slot and use an NVMe SSD as an internal system drive.

The same idea also applies to the TerraMaster F2-220. Although the F2-220 and F2-221 use different platforms, a fnNAS forum test shows that F3 Backplane V1.1 can detect NVMe on the F2-220, and the NVMe drive is visible inside the OS installer. The extra work is that the old BIOS may not support booting from NVMe.

Summary

The F2-221 backplane connector contains:

Signals for two native SATA ports
12V, 5V, 3.3V, and GND
SATA drive power-control related signals
PERST#
At least one usable PCIe Gen2 x1 signal group
Partial clues for a second PCIe signal group, but not fully verified

PCIe1 can be used to expose an M.2 M-key NVMe slot. In testing, the NVMe drive runs at PCIe Gen2 x1, and the BIOS can detect and boot from it.

F2-220 testing points in the same direction: the hardware can detect NVMe, but the BIOS boot stage may require injecting an NVMe module, and the boot entry may appear as PATA.

Backplane Connector Pinout

The connector has B/A sides. ? means unknown or unconnected, and NC means not connected.

Pin	B side	A side
1	12V	?
2	12V	12V
3	12V	12V
4	GND	GND
5	SATA1 A+	SATA1 B+
6	SATA1 A-	SATA1 B-
7	GND	NC
8	5V	5V
9	5V	5V
10	?	5V
11	?	?
12	3.3V	GND
13	GND	3.3V
14	SATA2 A+	3.3V
15	SATA2 A-	GND
16	GND	SATA2 B+
17	PERST#	SATA2 B-
18	GND	GND
19	PCIe1 TX+	NC
20	PCIe1 TX-	GND
21	GND	PCIe1 RX+
22	GND	PCIe1 RX-
23	PCIe1 REFCLK+	GND
24	PCIe1 REFCLK-	GND
25	GND	PCIe2 RX+
26	GND	PCIe2 RX-
27	PCIe2 TX+	GND
28	PCIe2 TX-	GND
29	GND	PCIe2 REFCLK+
30	?	PCIe2 REFCLK-
31	?	GND
32	GND	?

PCIe1 has higher practical reference value. PCIe2 is not fully verified and should only be treated as a clue, not a reliable design basis.

Signal Source Reasoning

The stock F2-221 dual-bay backplane does not include a PCIe-to-SATA controller. SATA signals go directly from the motherboard connector into the backplane. The extra PCIe signals are mainly inferred from other multi-bay models in the same product family.

The TerraMaster F5-422 backplane uses two ASMedia ASM1061 chips. ASM1061 is a PCIe Gen2 x1 to dual-SATA controller. Combined with the Intel J3355 having 2 SATA ports and 6 PCIe Gen2 lanes, this suggests that multi-bay models expand SATA ports through PCIe.

Therefore, it is reasonable for the F2-221 motherboard connector to retain PCIe signals. The vendor likely reuses motherboard designs across models with different bay counts and changes functionality through the backplane.

PCIe Differential Pair Identification

PCIe differential pairs often go into inner layers after vias, so photos alone cannot trace the complete routing. One useful rule is that, in traditional PCIe designs, TX differential pairs usually have AC coupling capacitors.

The direction must be viewed in reverse:

TX from the ASM1061 controller’s perspective corresponds to RX on the CPU or motherboard side.
RX from the ASM1061 controller’s perspective corresponds to TX on the CPU or motherboard side.
REFCLK needs to be judged together with neighboring differential pairs and routing location.

This kind of pinout is better treated as hardware reverse-engineering material, not as an official specification.

Validation

F3 Backplane designs based on this pinout have completed the following validation:

The original two SATA drive bays remain usable.
PCIe1 can be routed to an M.2 M-key slot.
The NVMe SSD can be detected by BIOS.
The NAS can boot directly from the NVMe SSD.
btrfs scrub found no disk errors.
The system ran from the NVMe SSD for weeks without obvious issues.

The test NVMe SSD was a Patriot P300 128GB. hdparm result:

1
2
3

/dev/nvme0n1:
 Timing cached reads:   4554 MB in  2.00 seconds = 2279.68 MB/sec
 Timing buffered disk reads: 1222 MB in  3.00 seconds = 407.22 MB/sec

This speed matches the PCIe Gen2 x1 limitation. The goal is not to fully utilize NVMe performance, but to replace an external USB SSD with an internal system drive.

Notes

This pinout is useful as a reference for hardware reverse engineering and custom backplanes, but it should not be treated as official documentation.

The connector is not standard PCIe and cannot directly accept generic PCIe devices.
? pins are unverified and should not be connected to critical circuits casually.
PCIe2 is not fully verified and carries higher risk than PCIe1.
CLKREQ is not fully routed like a normal M.2 design, so ASPM may not work.
SATA power includes hot-swap related load switch and slow start logic; do not route only signal lines while ignoring power control.
If reproducing the design, measure your own motherboard and backplane again instead of relying only on photos.

Original project write-up: I made a new backplane for my Terramaster F2-221 NAS
F3 Backplane KiCad project: arnarg/f3_backplane
F3 Backplane pinout CSV: f3_backplane.csv
F2-220 compatibility test: 铁威马F2-220折腾飞牛OS过程

A Detailed Look at PCIe Bifurcation Modes

Sat, 02 May 2026 10:15:49 +0800

PCIe bifurcation is the process of splitting PCIe lanes. It answers a simple question: should a group of PCIe lanes from the CPU or chipset work as one wide link, or be split into multiple narrower links for different devices?

For example, a group of 16 PCIe lanes can be configured as x16, split into x8+x8, or split into x8+x4+x4. This is the basis behind a motherboard running one graphics slot at full x16, two graphics slots at x8 each, or one graphics slot plus two CPU-attached M.2 slots.

What Is a PCIe Lane

PCIe is a serial bus. Each lane consists of differential signaling pairs and can be treated as an independent high-speed data channel. Multiple lanes can be bonded together to form a wider link:

Link width	Common use
`x1`	Network cards, sound cards, capture cards, USB expansion cards
`x4`	NVMe SSDs and some high-speed expansion cards
`x8`	Secondary graphics slots, RAID cards, network cards
`x16`	Primary graphics slot

PCIe link widths usually grow in powers of two, so common widths are x1, x2, x4, x8, and x16. On consumer motherboards, x1, x4, x8, and x16 are the ones you see most often.

The physical slot length is not the same as the actual link width. A long x16 slot may only be wired for x4 or x8; an M.2 slot is usually x4, but whether it connects to the CPU or chipset also matters.

When Bifurcation Happens

PCIe device initialization can be roughly divided into several stages:

Decide PCIe bifurcation, meaning how the lanes are split.
Run Root Port Training to train link speed and width.
Perform PCI enumeration so the system can discover devices.
Configure PCIe features such as power management, error reporting, and timeout control.

Bifurcation happens very early. The system must first know whether a group of lanes is one x16, two x8 links, or several x4 links before later Training and enumeration know how many Root Ports should be handled.

When bifurcation is configured incorrectly, common symptoms include:

An expansion card only detects one SSD.
Devices disappear after a riser or adapter card is installed.
A graphics card link width drops from x16 to x8.
The expected bifurcation option is missing from the BIOS.
The motherboard manual says a split mode is supported, but only on a specific slot or with a specific CPU.

Mode One: Hard Strap

Hard Strap is a hardware method. The motherboard uses fixed pins, pull-up or pull-down resistors, or wiring to determine the PCIe split mode at the hardware level.

This is common for CPU-attached PCIe lanes on consumer desktop platforms. For example, if the CPU provides one group of x16 lanes, the motherboard vendor can design the board as:

Configuration	Typical use
`x16`	One primary graphics slot
`x8+x8`	Two graphics slots
`x8+x4+x4`	One graphics slot plus two CPU-attached M.2 slots

Hard Strap is stable, simple, and low-cost. The motherboard vendor decides lane routing during PCB design, and users usually cannot freely change it in the BIOS afterward.

Its downside is poor flexibility. Once the board layout is fixed, a slot designed only as x16 cannot become x4+x4+x4+x4 unless the PCB is redesigned. That is why many consumer motherboards do not expose bifurcation options in the BIOS even if the CPU theoretically supports splitting.

For ordinary users, the most direct takeaway is this: whether a board supports PCIe bifurcation depends first on motherboard design, not only on CPU specifications.

Mode Two: Soft Strap

Soft Strap is a software-configured method, but it does not necessarily mean a user-facing BIOS menu option. In many cases, this configuration is stored in the BIOS image or platform description area and is set by the motherboard vendor before shipping.

PCIe Root Ports under the chipset often use a similar approach. Based on the actual board routing, the vendor can configure some Root Ports as independent x1 ports, or combine them into x2 or x4. These settings are usually fixed in the BIOS image and take effect during platform initialization.

Soft Strap has several traits:

Some settings can be adjusted without changing the PCB.
The configuration usually takes effect during early initialization.
Changes generally require reflashing the BIOS or at least rebooting.
The user interface may not expose the related options.

This is why two motherboards with similar-looking hardware can distribute PCIe slots, M.2 slots, and onboard devices differently depending on BIOS version or vendor configuration.

Soft Strap is still not magic. It can only adjust within the limits of the existing hardware routing; it cannot assign lanes to a slot that is not physically connected to them.

Mode Three: Wait For BIOS

Wait For BIOS is the more flexible approach. Before PCIe Training begins, the platform waits for the BIOS to write the relevant registers, and the BIOS decides how wide each group of lanes should be.

This is common on more expandable platforms, such as workstations, servers, and some Xeon platforms. These platforms provide more lanes and more complex slot combinations. If everything were fixed in hardware, motherboard adaptability would be much worse.

The advantage of Wait For BIOS is flexibility:

The BIOS can offer options such as x16, x8+x8, x8+x4+x4, and x4+x4+x4+x4.
One motherboard can adapt to different expansion cards.
It is better suited for multi-NVMe adapters, PCIe backplanes, and server riser cards.
Users can adjust the layout based on device count and bandwidth needs.

The cost is that the platform and BIOS must work together. The CPU or chipset must support the desired split, the motherboard routing must match it, and the BIOS must expose or configure it. If any of those pieces is missing, users may not see usable bifurcation settings.

Common Split Combinations

Different platforms support different combinations, but common split modes look like this:

Original link	Common split	Typical use
`x16`	`x16`	Single graphics card
`x16`	`x8+x8`	Dual graphics cards, or GPU plus high-speed expansion card
`x16`	`x8+x4+x4`	GPU plus two NVMe SSDs
`x16`	`x4+x4+x4+x4`	Four-drive NVMe adapter
`x8`	`x4+x4`	Dual NVMe drives or dual-port high-speed expansion
`x4`	`x2+x2` or multiple `x1` links	Less common; depends on platform support

In DIY builds, the most common request is splitting one x16 slot into x4+x4+x4+x4 for a four-M.2 adapter card. The key detail is that cheap adapter cards without a controller chip only physically route the slot to multiple M.2 connectors. The card itself does not split PCIe lanes.

If the motherboard does not support x4+x4+x4+x4, such an adapter usually detects only the first SSD. To use a multi-drive card on a board without bifurcation support, you need an expansion card with a PCIe Switch chip, which costs much more.

Bifurcation vs PCIe Switch

Bifurcation splits existing upstream lanes into multiple downstream ports. It does not increase the number of lanes; it only changes how they are allocated.

A PCIe Switch is more like a PCIe switching chip. It connects one upstream link to multiple downstream devices, so the system can see more devices. It also cannot create extra upstream bandwidth out of nothing, but it can solve the problem of attaching multiple devices when the motherboard does not support lane splitting.

The difference can be summarized like this:

Solution	Requires motherboard bifurcation support	Cost	Suitable scenario
Chipless M.2 adapter	Yes	Low	Motherboard supports `x4+x4+x4+x4`
Expansion card with PCIe Switch	Not always	High	Board does not support splitting but needs multiple devices

Before buying a multi-M.2 expansion card, check whether the motherboard BIOS supports the required split mode. A specification that only says “supports PCIe x16 slot” does not mean it can recognize four drives at once.

Buying and Troubleshooting Advice

If you want to use PCIe bifurcation, check things in this order:

Confirm that the CPU or platform supports the target split mode.
Check the motherboard manual to see whether the target slot supports x8+x8, x8+x4+x4, or x4+x4+x4+x4.
Enter the BIOS and look for options such as PCIe bifurcation, PCIe lane configuration, or slot configuration.
Confirm whether the expansion card is a chipless adapter or a card with a PCIe Switch.
Check whether fully populating devices shares lanes with M.2, SATA, onboard networking, or other devices.
After booting into the OS, use tools to inspect actual link width and device enumeration.

If an expansion card detects only one drive, check the BIOS split option first. If the BIOS has no related setting, it is probably not a driver issue; the motherboard is likely not splitting that group of lanes into multiple devices.

If all devices are detected but speed is wrong, then check link Training. Cable quality, adapter card quality, slot routing, PCIe generation, and device compatibility can all cause a link to fall from Gen4 to Gen3, or even lower.

Summary

PCIe bifurcation is about deciding how lanes are organized during early PCIe initialization. Hard Strap fixes the layout in hardware, Soft Strap uses platform configuration, and Wait For BIOS lets the BIOS set the mode before link training.

For ordinary PC builders, the three most important conclusions are:

A physical x16 slot does not necessarily split into multiple x4 links.
Chipless multi-M.2 adapter cards depend on motherboard bifurcation support.
Split support depends on the CPU, motherboard routing, and BIOS options together.

Once you understand these points, x16, x8+x8, and x4+x4+x4+x4 in a motherboard spec sheet stop being just slot-length labels. They become clues for judging whether the board can meet your actual expansion needs.

LGA1851 Z990/W980/Q970/Z970/B960/Z890/W880/Q870/B860/H810 Motherboard Lane Reference

Thu, 30 Apr 2026 00:08:21 +0800

The expansion capability of a motherboard may look like PCIe slots, M.2, SATA, USB, network cards, audio cards, and other interfaces. Underneath, it is really a question of which lanes are provided by the CPU and chipset, then how the motherboard vendor assigns them to different interfaces.

So when reading a motherboard specification, it is not enough to ask “how many M.2 slots” or “how many USB-C ports” it has. The more important questions are where those interfaces come from: CPU direct connection or chipset forwarding; whether they are dedicated or shared with other interfaces; whether they are PCIe 5.0 or PCIe 4.0/3.0; and whether SATA is independent or provided by internal chipset resources.

This article rewrites the original spreadsheet into text form and summarizes the general composition of each chipset platform.

The resource counts below come from lane-row statistics in the original spreadsheet. Chip Link is counted only on the CPU side to avoid doubling the upstream link; CPU-variant or example sub-tables below some sheets are not counted again.

Understanding Lane Sources

The lanes on a motherboard can usually be divided into three categories.

The first category is CPU direct lanes.

These lanes have low latency and high bandwidth. They are usually used for the main graphics slot, the first M.2 slot, some USB4/Thunderbolt resources, display output, and the link between the CPU and chipset. On consumer platforms, high-end interfaces are usually allocated here first.

The second category is chipset expansion lanes.

The chipset connects to the CPU through DMI, PCIe, or a dedicated link, then provides additional PCIe, SATA, USB, wired networking, wireless networking, audio, and low-speed controller resources. Chipset-side interfaces are numerous, but they share the upstream link, so it is not ideal to put every high-load device behind the chipset.

The third category is interfaces converted through onboard controllers.

For example, 2.5G/10G network controllers, extra SATA controllers, USB hub or expansion chips, Thunderbolt/USB4 controllers, and audio chips usually consume PCIe, USB, or other low-speed lanes. When reading a motherboard topology, remember that these controllers also consume resources behind the scenes.

Intel Consumer Platforms

Intel consumer platforms usually follow a “CPU direct lanes + DMI to chipset + chipset-expanded I/O” structure.

The CPU side mainly handles:

Integrated graphics display output
PCIe lanes for the graphics slot
CPU-direct M.2 or high-bandwidth PCIe lanes
The DMI link from CPU to chipset

The chipset side handles many peripherals:

PCIe 4.0/3.0 expansion lanes
SATA
USB 2.0, USB 5G, USB 10G, USB 20G
Wired networking, wireless networking, audio, management controllers, and other onboard devices

LGA1851 / 800 Series and Future 900 Series

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
Z990	PCIe 5.0 x24, USB4/TBT x2, Display x2	DMI 5.0 x4	PCIe 5.0 x12, PCIe 4.0 x12, USB 10G x10, USB 2.0 x4
W980	PCIe 5.0 x24, USB4/TBT x2, Display x2	DMI 5.0 x4	PCIe 5.0 x12, PCIe 4.0 x12, USB 10G x10, USB 2.0 x4
Q970	PCIe 5.0 x24, USB4/TBT x2, Display x2	DMI 5.0 x4	PCIe 5.0 x8, PCIe 4.0 x12, USB 10G x8, USB 5G x2, USB 2.0 x4
Z970	PCIe 5.0 x20, USB4/TBT x1, Display x3	DMI 5.0 x2	PCIe 4.0 x14, USB 10G x4, USB 5G x2, USB 2.0 x6, SATA x4
B960	PCIe 5.0 x20, USB4/TBT x1, Display x3	DMI 5.0 x2	PCIe 4.0 x14, USB 10G x4, USB 5G x2, USB 2.0 x6, SATA x4
Z890	PCIe 5.0 x20, PCIe 4.0 x4, USB4/TBT x2, Display x2	DMI 4.0 x8	PCIe 4.0 x24, USB 10G x10, USB 2.0 x4
W880	PCIe 5.0 x20, PCIe 4.0 x4, USB4/TBT x2, Display x2	DMI 4.0 x8	PCIe 4.0 x24, USB 10G x10, USB 2.0 x4
Q870	PCIe 5.0 x20, PCIe 4.0 x4, USB4/TBT x2, Display x2	DMI 4.0 x8	PCIe 4.0 x20, USB 10G x8, USB 5G x2, USB 2.0 x4
B860	PCIe 5.0 x20, USB4/TBT x1, Display x3	DMI 4.0 x4	PCIe 4.0 x14, USB 10G x4, USB 5G x2, USB 2.0 x6, SATA x4
H810	PCIe 5.0 x16, USB4/TBT x1, Display x2	DMI 4.0 x4	PCIe 4.0 x8, USB 10G x2, USB 5G x2, USB 2.0 x6, SATA x4

For LGA1851 platforms such as Z890, W880, Q870, B860, and H810, the general idea is to keep high-speed core resources on the CPU side and place large amounts of I/O on the chipset side.

Z-series chipsets target high-end consumer boards. They usually enable CPU overclocking, memory overclocking, and more flexible graphics-lane bifurcation. W/Q series parts lean toward workstation or business-management scenarios, with more emphasis on ECC, stability, manageability, and onboard-device support. B/H series chipsets are more mainstream or entry-level, with more conservative lane counts, bifurcation capability, and overclocking support.

This kind of platform can be summarized as:

The CPU provides display output, Thunderbolt/USB4-related resources, PCIe 5.0 graphics lanes, and direct storage lanes
The chipset provides additional PCIe, SATA, USB, wired networking, wireless networking, and audio resources
High-end chipsets mainly differ in lane count, USB capabilities, PCIe generation, and bifurcation support

On a high-end board such as Z890, the first graphics slot and at least one M.2 slot usually come from the CPU, while other M.2 slots, SATA ports, USB ports, and onboard controllers mostly hang off the chipset.

LGA1700 / 600 and 700 Series

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
Z790	PCIe 5.0 x16, PCIe 4.0 x4, Display x4	DMI 4.0 x8	PCIe 4.0 x20, PCIe 3.0 x8, USB 10G x10, USB 2.0 x4
H770	PCIe 5.0 x16, PCIe 4.0 x4, Display x4	DMI 4.0 x8	PCIe 4.0 x16, PCIe 3.0 x8, USB 10G x4, USB 5G x4, USB 2.0 x6
B760	PCIe 4.0 x20, Display x4	DMI 4.0 x4	PCIe 4.0 x10, PCIe 3.0 x4, USB 10G x4, USB 5G x2, USB 2.0 x6, SATA x4
Z690	PCIe 5.0 x16, PCIe 4.0 x4, Display x4	DMI 4.0 x8	PCIe 4.0 x12, PCIe 3.0 x16, USB 10G x10, USB 2.0 x4
W680	PCIe 5.0 x16, PCIe 4.0 x4, Display x4	DMI 4.0 x8	PCIe 4.0 x12, PCIe 3.0 x16, USB 10G x10, USB 2.0 x4
Q670	PCIe 5.0 x16, PCIe 4.0 x4, Display x4	DMI 4.0 x8	PCIe 4.0 x12, PCIe 3.0 x12, USB 10G x8, USB 5G x2, USB 2.0 x4
H670	PCIe 5.0 x16, PCIe 4.0 x4, Display x4	DMI 4.0 x8	PCIe 4.0 x12, PCIe 3.0 x12, USB 10G x4, USB 5G x4, USB 2.0 x6
B660	PCIe 4.0 x20, Display x4	DMI 4.0 x4	PCIe 4.0 x6, PCIe 3.0 x8, USB 10G x4, USB 5G x2, USB 2.0 x6, SATA x4
H610	PCIe 4.0 x16, Display x3	DMI 4.0 x4	PCIe 3.0 x8, USB 10G x2, USB 5G x2, USB 2.0 x6, SATA x4, GbE x1

LGA1700 covers 12th, 13th, and 14th Gen Core processors. Typical chipsets include Z790, H770, B760, H610, and the previous Z690, H670, B660, and H610.

The main characteristics of this generation are:

The CPU side provides PCIe 5.0 lanes for graphics
The CPU side also provides a common set of PCIe 4.0 storage lanes
The chipset connects to the CPU through DMI
Higher-end chipsets have more PCIe, USB, and SATA resources
Z series supports CPU overclocking, while B/H series usually does not

Z790/Z690 have richer chipset resources and are better suited for boards with multiple M.2 slots, many USB ports, and multiple expansion cards. B760/B660 are more mainstream and usually cover one graphics card, two or three M.2 slots, several SATA ports, and normal USB needs. H610 is much more limited and is aimed at entry-level builds.

When reading an LGA1700 board, focus on where the M.2 slots come from. A CPU-direct M.2 slot is usually better for the OS drive or a high-performance SSD. Chipset-side M.2 slots can be numerous, but they share the DMI upstream link.

LGA1200 / 400 and 500 Series

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
Z590	PCIe 4.0 x20, Display x3	DMI 3.0 x8	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
W580	PCIe 4.0 x20, Display x3	DMI 3.0 x8	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
Q570	PCIe 4.0 x20, Display x3	DMI 3.0 x8	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
H570	PCIe 4.0 x20, Display x3	DMI 3.0 x8	PCIe 3.0 x20, USB 10G x4, USB 5G x4, USB 2.0 x6, SATA x2
B560	PCIe 4.0 x20, Display x3	DMI 3.0 x4	PCIe 3.0 x12, USB 10G x4, USB 5G x2, USB 2.0 x6, SATA x6
H510	PCIe 4.0 x16, Display x2	DMI 3.0 x4	PCIe 3.0 x6, USB 5G x4, USB 2.0 x6, SATA x4, GbE x1
Z490	PCIe 3.0 x16, Display x3, N/A (CML CPU) x4	DMI 3.0 x4	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
W480	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
Q470	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
H470	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x20, USB 10G x4, USB 5G x4, USB 2.0 x6, SATA x2
B460	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x12, USB 5G x8, USB 2.0 x4, SATA x6
H410	PCIe 3.0 x16, Display x2	DMI 3.0 x4	PCIe 3.0 x6, USB 5G x4, USB 2.0 x6, SATA x4, GbE x1

LGA1200 covers 10th and 11th Gen Core processors. Typical chipsets include Z590, W580, Q570, H570, B560, H510, as well as Z490, H470, B460, and H410.

This platform sits in the transition from PCIe 3.0 to PCIe 4.0. With 11th Gen Core processors and 500-series boards, the CPU side can provide PCIe 4.0. With 10th Gen Core and 400-series platforms, the system mostly remains on PCIe 3.0.

The overall structure is:

The CPU side provides graphics lanes and display output
Some combinations support CPU-direct PCIe 4.0 storage
The chipset side provides PCIe 3.0, SATA, USB, and onboard-device resources
Z series provides more complete overclocking and lane-allocation capability

For old-system upgrades, the most important thing is the pairing between CPU generation and chipset. Not every LGA1200 board can fully use PCIe 4.0, and not every M.2 slot comes from the CPU.

LGA115X / Earlier Platforms

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
Z390	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
Q370	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x24, USB 10G x6, USB 2.0 x4
H370	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x20, USB 10G x4, USB 5G x4, USB 2.0 x6, SATA x2
B365	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x20, USB 5G x8, USB 2.0 x6, SATA x2
B360	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x12, USB 10G x4, USB 5G x2, USB 2.0 x6, SATA x6
H310	PCIe 3.0 x16, Display x2	DMI 2.0 x4	PCIe 2.0 x6, USB 5G x4, USB 2.0 x6, SATA x4, GbE x1
Z370 / Z270	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x24, USB 5G x6, USB 2.0 x4
Q270	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x24, USB 5G x6, USB 2.0 x4
H270	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x20, USB 5G x8, USB 2.0 x6, SATA x2
Q250	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x14, USB 5G x8, USB 2.0 x6, SATA x4, GbE x1
B250	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x12, USB 5G x6, USB 2.0 x6, SATA x6, GbE x1
Z170	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x20, USB 5G x6, USB 2.0 x4
Q170	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x20, USB 5G x6, USB 2.0 x4
H170	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x16, USB 5G x8, USB 2.0 x6, SATA x2
Q150	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x10, USB 5G x8, USB 2.0 x6, SATA x4
B150	PCIe 3.0 x16, Display x3	DMI 3.0 x4	PCIe 3.0 x8, USB 5G x6, USB 2.0 x6, SATA x6, GbE x1
H110	PCIe 3.0 x16, Display x2	DMI 2.0 x4	PCIe 2.0 x6, USB 5G x4, USB 2.0 x6, SATA x4, GbE x2
Z97 / H97 / Z87 / H87	PCIe 3.0 x16, Display x3	DMI 2.0 x4	PCIe 2.0 x10, USB 5G x4, USB 2.0 x8, SATA x4
B85	PCIe 3.0 x16, Display x3	DMI 2.0 x4	PCIe 2.0 x8, USB 5G x4, USB 2.0 x8, SATA x6
H81	PCIe 2.0 x16, Display x2	DMI 2.0 x4	PCIe 2.0 x6, USB 5G x2, USB 2.0 x8, SATA x4
Z77 / Z75 / H77	PCIe 3.0 x16, Display x3	DMI 2.0 x4	PCIe 2.0 x8, USB 5G x4, USB 2.0 x10, SATA x6
B75	PCIe 3.0 x16, Display x3	DMI 2.0 x4	PCIe 2.0 x8, USB 5G x4, USB 2.0 x8, SATA x6
Z68 / H67	PCIe 2.0 x16, Display x2	DMI 2.0 x4	PCIe 2.0 x8, USB 2.0 x14, SATA x6
P67	PCIe 2.0 x16	DMI 2.0 x4	PCIe 2.0 x8, USB 2.0 x14, SATA x6
B65	PCIe 2.0 x16, Display x2	DMI 2.0 x4	PCIe 2.0 x8, USB 2.0 x12, SATA x6
H61	PCIe 2.0 x16, Display x2	DMI 2.0 x4	PCIe 2.0 x6, USB 2.0 x10, SATA x4
H57	PCIe 2.0 x16, Display x2	DMI 1.0 x4	PCIe 2.0 x8, USB 2.0 x14, SATA x6
P55	PCIe 2.0 x16	DMI 1.0 x4	PCIe 2.0 x8, USB 2.0 x14, SATA x6
H55 / B55	PCIe 2.0 x16, Display x2	DMI 1.0 x4	PCIe 2.0 x6, USB 2.0 x12, SATA x6

LGA115X spans many generations, including Z390, Q370, H370, B365, B360, H310, Z270, H270, B250, Z170, H170, B150, H110, and more.

These platforms share several characteristics:

The CPU side usually mainly provides PCIe 3.0 graphics lanes and display output
High-speed storage, SATA, USB, networking, and many other resources depend heavily on the PCH chipset
Chipset-side PCIe is mostly PCIe 3.0 or earlier
Chipset differences mainly come from PCIe lane count, SATA count, USB count, and overclocking support

Z series chipsets are suited to overclocking and richer expansion. H/B/Q series parts are reduced according to positioning. Because these platforms are older, M.2 and USB-C support often depends on additional motherboard-vendor design, so the chipset name alone is not enough.

Intel HEDT and Workstation Platforms

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
W790	PCIe 5.0 x112	DMI 4.0 x8	PCIe 4.0 x12, PCIe 3.0 x16, USB 10G x10, USB 2.0 x4
X299	PCIe 3.0 x48	DMI 3.0 x4	PCIe 3.0 x24, USB 5G x6, USB 2.0 x4
X99	PCIe 3.0 x40	DMI 2.0 x4	PCIe 2.0 x8, USB 5G x4, USB 2.0 x8, SATA x8
X79	PCIe 3.0 x40	DMI 2.0 x4	PCIe 2.0 x8, USB 2.0 x14, SATA x6
X58	-	-	PCIe 2.0 x36, USB 2.0 x12, SATA x6, PCIe 1.1 x6

The biggest difference between Intel HEDT/workstation platforms and consumer platforms is the much larger number of CPU direct lanes.

W790 targets Xeon W and provides many PCIe 5.0 lanes on the CPU side, along with wider memory channels, more complete ECC/RECC capability, and multi-expansion-card scenarios. Older HEDT platforms such as X299 mainly rely on large numbers of CPU-direct PCIe 3.0 lanes.

The logic of these platforms is:

The CPU directly handles graphics cards, capture cards, RAID cards, high-speed network cards, multiple M.2/U.2 devices, and other high-bandwidth devices
The chipset mainly handles SATA, USB, management interfaces, and low-speed peripherals
The value of the platform is not “how many lanes the chipset has,” but how many direct PCIe lanes the CPU itself can allocate

For multiple expansion cards or many high-speed SSDs, HEDT/workstation platforms are more comfortable than consumer platforms because they do not need to squeeze many high-bandwidth devices through the chipset upstream link.

AMD AM5 Platform

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
X870E	PCIe 5.0 x20, USB4/TBT x6, USB 10G x2, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x12, PCIe 3.0 x8, USB 10G x12, USB 2.0 x12, Granite Ridge / Raphael x2
X870	PCIe 5.0 x20, USB4/TBT x6, USB 10G x2, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x8, PCIe 3.0 x4, USB 10G x6, USB 2.0 x6, Phoenix x2
B850	PCIe 5.0 x24, USB 10G x4, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x8, PCIe 3.0 x4, USB 10G x6, USB 2.0 x6, Phoenix2 x2
B840	PCIe 4.0 x24, USB 10G x4, USB 2.0 x1, Display x1	PCIe 3.0 x4	PCIe 3.0 x10, USB 10G x2, USB 5G x2, USB 2.0 x6, SATA x4
X670E	PCIe 5.0 x24, USB 10G x4, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x12, PCIe 3.0 x8, USB 10G x12, USB 2.0 x12
X670	PCIe 5.0 x8, PCIe 4.0 x16, USB 10G x4, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x12, PCIe 3.0 x8, USB 10G x12, USB 2.0 x12
B650E	PCIe 5.0 x24, USB 10G x4, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x8, PCIe 3.0 x4, USB 10G x6, USB 2.0 x6
B650	PCIe 5.0 x4, PCIe 4.0 x20, USB 10G x4, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x8, PCIe 3.0 x4, USB 10G x6, USB 2.0 x6
A620	PCIe 4.0 x24, USB 10G x4, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 3.0 x8, USB 10G x2, USB 5G x2, USB 2.0 x6
A620A	PCIe 4.0 x24, USB 10G x4, USB 2.0 x1, Display x1	PCIe 3.0 x4	PCIe 3.0 x8, USB 10G x2, USB 5G x2, USB 2.0 x6
PRO 665	PCIe 5.0 x4, PCIe 4.0 x20, USB 10G x4, USB 2.0 x1, Display x1	PCIe 4.0 x4	PCIe 4.0 x8, PCIe 3.0 x4, USB 10G x6, USB 2.0 x6
PRO 600	PCIe 4.0 x28, USB 10G x4, USB 2.0 x1, Display x1	-	-

Typical AMD AM5 chipsets include X870E, X870, B850, B840, and the previous X670E, X670, B650E, B650, and A620.

AM5 has several clear characteristics:

The CPU side provides PCIe lanes for graphics
The CPU side provides high-speed M.2 lanes
The CPU side also integrates some USB, display output, and chipset-link resources
High-end E-suffix platforms emphasize PCIe 5.0 support for graphics or storage
The chipset continues to expand PCIe, SATA, USB, and onboard-device resources

High-end platforms such as X870E/X670E usually have more high-speed resources and are better suited to multiple M.2 devices, more USB4/USB-C ports, and high-end graphics cards. X870/X670 keep strong expansion capability but may be more restrained in PCIe 5.0 allocation. B850/B650 target mainstream builds, usually with one graphics slot, one or more M.2 slots, and chipset-side expansion interfaces. A620/B840 are entry-level and reduce lane count and overclocking capability.

When reading AM5 boards, the most important thing is to identify where PCIe 5.0 is allocated: to the graphics slot, to M.2, or to both. Even with the same chipset name, motherboard vendors may allocate lanes differently.

AMD AM4 Platform

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
X570(S)	PCIe 4.0 x20, USB 10G x4, Display x4	PCIe 4.0 x4	PCIe 4.0 x16, USB 10G x8, USB 2.0 x4, SATA x4
B550	PCIe 4.0 x20, USB 10G x4, Display x4	PCIe 3.0 x4	PCIe 3.0 x10, USB 10G x2, USB 5G x2, USB 2.0 x6, SATA x4
A520	PCIe 3.0 x20, USB 10G x4, Display x4	PCIe 3.0 x4	PCIe 3.0 x6, USB 10G x1, USB 5G x2, USB 2.0 x6, SATA x2
X470 / X370	PCIe 3.0 x20, USB 5G x4, Display x4	PCIe 3.0 x4	PCIe 3.0 x4, PCIe 2.0 x8, USB 10G x2, USB 5G x6, USB 2.0 x6, SATA x4
B450 / B350	PCIe 3.0 x20, USB 5G x4, Display x4	PCIe 3.0 x4	PCIe 3.0 x2, PCIe 2.0 x6, USB 10G x2, USB 5G x2, USB 2.0 x6, SATA x2
A320	PCIe 3.0 x20, USB 5G x4, Display x4	PCIe 3.0 x4	PCIe 2.0 x4, USB 10G x1, USB 5G x2, USB 2.0 x6, SATA x4

AM4 had a very long life. Typical chipsets include X570/X570S, B550, A520, and older X470, B450, X370, B350, A320, and more.

AM4 can be understood like this:

The CPU provides graphics lanes, some USB, display output, and direct storage lanes
X570 is the strongest generation in expansion capability, with higher-spec PCIe resources on the chipset side as well
B550 can have PCIe 4.0 on the CPU side, but the chipset side is usually more like PCIe 3.0 expansion
Entry-level chipsets such as A520/A320 mainly cover basic PCIe, SATA, and USB needs

AM4 platforms vary greatly. A high-end X570 motherboard and an entry-level A320 board are not in the same class, even though both are AM4. When reading older platforms, also check whether the CPU has integrated graphics, whether the motherboard BIOS supports the target CPU, and how M.2/PCIe resources are actually allocated.

AMD Threadripper Platform

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
X399	PCIe 3.0 x60, USB 5G x8	PCIe 3.0 x4	PCIe 3.0 x4, PCIe 2.0 x8, USB 10G x2, USB 5G x6, USB 2.0 x6, SATA x4
TRX40	PCIe 4.0 x56, USB 10G x4	PCIe 4.0 x8	PCIe 4.0 x16, USB 10G x8, USB 2.0 x4, SATA x4
WRX80	PCIe 4.0 x120, USB 10G x4	PCIe 4.0 x8	PCIe 4.0 x16, USB 10G x8, USB 2.0 x4, SATA x4
TRX50	PCIe 5.0 x48, PCIe 4.0 x28, USB 10G x4	PCIe 4.0 x4	PCIe 4.0 x8, USB 20G x1, USB 10G x4, USB 2.0 x6, SATA x4
WRX90	PCIe 5.0 x124, PCIe 3.0 x8, USB 10G x4	PCIe 4.0 x4	PCIe 4.0 x8, USB 20G x1, USB 10G x4, USB 2.0 x6, SATA x4

Threadripper platforms include X399, TRX40, WRX80, TRX50, WRX90, and other stages.

Their biggest difference from AM4/AM5 is the huge amount of CPU direct resources. Early X399 already targeted multiple graphics cards, many NVMe devices, and multiple expansion cards. TRX40 later strengthened PCIe 4.0. WRX80/WRX90 are more workstation-oriented, supporting more memory channels, ECC/RECC, and large amounts of professional expansion.

This kind of platform can be summarized as:

The CPU provides many PCIe lanes that directly connect graphics cards, SSDs, network cards, capture cards, and professional controllers
The chipset handles USB, SATA, low-speed I/O, and some supplementary expansion
High-end workstation models care more about memory channels, ECC, manageability, and parallel use of many devices

The key question for a Threadripper board is not simply “can it plug in many devices,” but how those devices are grouped, which slots share lanes, which M.2/U.2 devices come from the CPU, and which controllers hang off the chipset.

AMD EPYC Platform

Resource Count Quick Reference

Chipset/Platform	Main CPU-side resources	Upstream/Interconnect	Main chipset-side resources
7001	PCIe 3.0 x128, USB 5G x4	-	-
7002	PCIe 4.0 x128, PCIe 2.0 x2, USB 5G x4	-	-
7003	PCIe 4.0 x128, PCIe 2.0 x2, USB 10G x4	-	-
4004 / 4005	PCIe 5.0 x28, USB 10G x4, USB 2.0 x1, Display x1	-	4004 / 4005 with Chipset x2
8004	PCIe 5.0 x96, PCIe 3.0 x8, USB 5G x4	-	-
9004	PCIe 5.0 x128, PCIe 3.0 x8, USB 5G x4	-	-
9005	PCIe 5.0 x128, PCIe 3.0 x8, USB 5G x4	-	-
7001 2P	PCIe 3.0 x64, USB 5G x4, Infinity Fabric x64	-	-
7001 2P	1 x4, 10 x4, 11 x4, 12 x4, 13 x4, 14 x4, 15 x4, 16 x4, 17 x4, 18 x4, 19 x4, 2 x4, 20 x4, 21 x4, 22 x4, 23 x4, 24 x4, 25 x4, 26 x4, 27 x4, 28 x4, 29 x4, 3 x4, 30 x4, 31 x4, 32 x4, 33 x4, 4 x4, 5 x4, 6 x4, 7 x4, 8 x4, 9 x4	-	34 x2
7002 2P	PCIe 4.0 x80, PCIe 2.0 x2, USB 5G x4, Infinity Fabric x48	-	-
7002 2P	1 x4, 10 x4, 11 x4, 12 x4, 13 x4, 14 x4, 15 x4, 16 x4, 17 x4, 18 x4, 19 x4, 2 x4, 20 x4, 21 x4, 22 x4, 23 x4, 24 x4, 25 x4, 26 x4, 27 x4, 28 x4, 29 x4, 3 x4, 30 x4, 31 x4, 32 x4, 33 x4, 34 x2, 4 x4, 5 x4, 6 x4, 7 x4, 8 x4, 9 x4	-	-
7003 2P	PCIe 4.0 x80, PCIe 2.0 x2, USB 10G x4, Infinity Fabric x48	-	-
7003 2P	1 x4, 10 x4, 11 x4, 12 x4, 13 x4, 14 x4, 15 x4, 16 x4, 17 x4, 18 x4, 19 x4, 2 x4, 20 x4, 21 x4, 22 x4, 23 x4, 24 x4, 25 x4, 26 x4, 27 x4, 28 x4, 29 x4, 3 x4, 30 x4, 31 x4, 32 x4, 33 x4, 34 x2, 4 x4, 5 x4, 6 x4, 7 x4, 8 x4, 9 x4	-	34 x2, 35 x4
9004 2P	PCIe 5.0 x80, PCIe 3.0 x8, USB 5G x4, Infinity Fabric x48	-	-
9004 2P	1 x4, 10 x4, 11 x4, 12 x4, 13 x4, 14 x4, 15 x4, 16 x4, 17 x4, 18 x4, 19 x4, 2 x4, 20 x4, 21 x4, 22 x4, 23 x4, 24 x4, 25 x4, 26 x4, 27 x4, 28 x4, 29 x4, 3 x4, 30 x4, 31 x4, 32 x4, 33 x4, 34 x4, 35 x4, 4 x4, 5 x4, 6 x4, 7 x4, 8 x4, 9 x4	-	-
9005 2P	PCIe 5.0 x80, PCIe 3.0 x8, USB 5G x4, Infinity Fabric x48	-	-

EPYC platforms are divided into single-socket and dual-socket configurations. The table includes generations such as 7001, 7002, 7003, 9004, and 9005.

EPYC is completely different from consumer platforms. It is not designed around “a chipset expanding many peripherals,” but around the large I/O resources of server CPUs.

A single-socket EPYC platform usually has:

A large number of CPU-direct PCIe lanes
Multiple PCIe root complexes or resource groups
Direct connection capability for network cards, NVMe devices, GPUs, accelerators, and RAID cards
Less dependence on a traditional consumer PCH

Dual-socket EPYC platforms also include Infinity Fabric links between CPUs. Some lanes must be used for CPU-to-CPU interconnect, so not all physical lanes can be freely assigned to external devices as on a single-socket system.

For dual-socket platforms, focus on:

Which PCIe slots and devices each CPU is responsible for
Which lanes are used for CPU-to-CPU interconnect
Whether devices are accessed across CPUs
How the motherboard allocates NVMe, network, and accelerator resources

Server platform lane configuration is more like a system topology diagram than an ordinary motherboard specification sheet. For storage servers, GPU servers, and virtualization hosts, these allocations directly affect bandwidth, latency, and NUMA access paths.

How to Read Horizontal Lane Diagrams

The original spreadsheet also includes horizontal lane diagrams for Intel 700 series and AMD 800 series. These diagrams turn abstract lane counts into concrete per-lane usage.

Read them in this order:

First look at the connection between CPU and chipset, such as DMI or PCIe
Then look at how CPU-side PCIe lanes are assigned to graphics, M.2, or USB4
Then look at how chipset-side PCIe, SATA, USB, wired networking, wireless networking, and other resources are arranged
Finally check which lanes are multiplexed or downgraded

These diagrams are more intuitive than ordinary specification tables because they explain why one interface may reduce or disable another.

What to Focus on When Choosing a Motherboard

The point of reading chipset lane configuration is to judge whether a motherboard fits your device combination.

For a normal gaming or office PC, focus on the graphics slot, one high-speed M.2 slot, enough USB ports, and networking. B-series or mid-range chipsets are usually enough.

For multiple SSDs, multiple expansion cards, capture cards, 10G networking, or high-speed external devices, focus on CPU direct lane count, chipset upstream bandwidth, and whether M.2 slots share resources with PCIe slots.

For workstations or servers, prioritize CPU direct PCIe count, memory channels, ECC support, NUMA topology, dual-socket interconnect, and motherboard slot allocation rather than just the chipset name.

Final Thought

A chipset is not an isolated chip. It is an I/O allocation scheme.

For consumer platforms, the focus is CPU-direct high-speed devices plus chipset-provided daily I/O. For HEDT and workstation platforms, the focus is the large number of direct lanes provided by the CPU itself. For server platforms, PCIe, memory, and CPU interconnect must be considered as a complete topology.

So when judging a motherboard’s expansion capability, do not only count interfaces. You should also check whether those interfaces come from the CPU or the chipset, whether they share lanes, and whether they will affect each other when the system is fully populated.

How Intel's ATX 3.0 Design Guide Classifies PCIe Auxiliary Power Connectors for GPUs

Thu, 23 Apr 2026 22:22:49 +0800

In ATX Version 3 Multi Rail Desktop Platform Power Supply Design Guide 2.1a, Intel groups the auxiliary power connectors used by PCI Express Add-in Card devices into three categories:

PCIe 2x3
PCIe 2x4
12V-2x6

In practice, the most common Add-in Card here is a discrete graphics card. The document also makes it clear that these connector types cover a power range from 75W all the way up to 600W.

1. The short version first

If you only want the key distinction, you can think of them like this:

2x3 corresponds to the familiar GPU 6-pin, rated for 75W
2x4 corresponds to the common GPU 8-pin, rated for 150W, and backward-compatible with 2x3
12V-2x6 is the newer high-power GPU connector, with support up to 600W

The real dividing line is not just wattage, but also this:

2x3 / 2x4 still follow the traditional auxiliary power approach
12V-2x6 folds high-power delivery, insertion-state detection, and sideband signaling into the standard itself

2. `PCIe 2x3`: the old 6-pin, defined here as `75W`

On this page, Intel defines the 2x3 Auxiliary Power Connector as an auxiliary power connector that can provide 75W for a PCIe add-in card.

The key details include:

The design target is 75W
The maximum rated value is 8.0A/pin
The cable gauge listed is 18 AWG
One Sense pin needs to be tied to ground so the graphics card can detect whether a 2x3 auxiliary power cable is connected

If you map it to today’s PC-building terminology, this is essentially the familiar GPU 6-pin auxiliary power connector.

3. `PCIe 2x4`: 8-pin, `150W`, and backward-compatible with `2x3`

The 2x4 Auxiliary Power Connector corresponds to the more common GPU 8-pin connector, and Intel gives it a target power level of 150W.

There are two especially important design points here:

A board-side 2x4 receptacle can accept either a 2x4 plug or a 2x3 plug
The graphics card uses SENSE0 and SENSE1 to identify which type of cable is actually plugged in

Intel gives the following detection logic:

`SENSE1`	`SENSE0`	Meaning
Ground	Ground	A `2x4` plug is inserted, so the graphics card may draw `150W` from the auxiliary connector
Open	Ground	A `2x3` plug is inserted, so the graphics card may draw only `75W`
Ground	Open	Reserved
Open	Open	No auxiliary power cable is connected

So a board-side 8-pin is not simply “a 6-pin with two extra pins.” It also carries the power-identification logic.

4. `12V-2x6`: the new high-power connector, up to `600W`

With 12V-2x6, the positioning changes completely. Intel directly defines it as a 12V power connector for PCIe add-in cards that can deliver up to 600W.

The main points in the document include:

12V-2x6 is not compatible with 2x3 or 2x4
Its primary power-contact pitch is 3.0 mm
The contact pitch of 2x3 and 2x4 is larger at 4.2 mm
This connector uses 12 large contacts for power delivery, plus 4 smaller contacts for sideband signals

Its cable requirements are also stricter than those of older connectors:

Power and ground wires use 16 AWG
All 12 main power pins must be fully wired, with no missing conductors
Sideband signal wires use 28 AWG
The main power pins are rated at 9.2A/pin

The document also requires an H++ marking on the connector body to indicate support for 9.2A/pin or higher.

The image above is Figure 5-3 on Intel’s page, corresponding to the 12V-2x6 Cable Plug Connector.

This one is Figure 5-5, corresponding to the 12V-2x6 PCB Header. Looking at the two diagrams together, it becomes much easier to see that this is no longer the traditional 6-pin/8-pin connector form.

5. Why `12V-2x6` is not the same as the early `12VHPWR`

Intel includes a dedicated section in this guide called 12V-2x6 vs. 12VHPWR.

Its conclusion is very clear:

Early 12VHPWR has been deprecated
PCIe CEM 5.1 switched to 12V-2x6
The two look broadly similar, but the newer connector adds several reliability improvements

The core changes mainly fall into two groups.

The first is mechanical structure:

The main power pins are longer
The sideband pins are shorter

The goal is to let the main power pins make contact first and break contact last, while the sideband signals only connect after the main power pins have been inserted deeply enough.

The second group is updated SENSE0 / SENSE1 logic:

The 150W level now requires SENSE0 and SENSE1 to be shorted together
When both signals are in the Open-Open state, the new spec defines that as 0W
In other words, if the plug is not fully inserted, or not inserted at all, a compliant graphics card should not draw power from that cable

That is also one of the reasons 12V-2x6 is considered more conservative and more robust than the early 12VHPWR.

6. What do the four `12V-2x6` sideband signals do?

On the sideband-signal page, Intel defines four signals for 12V-2x6:

SENSE0, required
SENSE1, required
CARD_PWR_STABLE, optional
CARD_CBL_PRES#, required on the graphics-card side and optional on the power-supply side

1. `SENSE0 / SENSE1`

These two signals tell the graphics card what power level the cable and power supply currently allow.

Intel provides the following power table:

`SENSE0`	`SENSE1`	Initial allowed power at startup	Maximum sustained power after software configuration
Ground	Ground	`375W`	`600W`
Open	Ground	`225W`	`450W`
Ground	Open	`150W`	`300W`
Short	Short	`100W`	`150W`
Open	Open	`0W`	`0W`

The key is not memorizing the table, but understanding this: 12V-2x6 is no longer just a binary “power/no power” connector. Through sideband signals, it explicitly encodes multiple power tiers to the graphics card.

2. `CARD_PWR_STABLE`

This is an optional signal, and it behaves a lot like a graphics-card feedback version of Power Good.

Intel defines it this way:

When the graphics card’s local critical power rails are within normal range, this signal stays open/high impedance
When the graphics card detects that those local critical rails are out of range, it actively pulls the signal low
If this signal is implemented, the power-supply side should pull it up to +3.3V through 4.7 kOhm

Put simply, it gives the power supply an extra fault-awareness input.

3. `CARD_CBL_PRES#`

This signal is more about connection detection:

It lets the power supply know that the 12V-2x6 cable really is connected to the graphics card and seated properly
In a modular power-supply setup, it can also help confirm whether the PSU-side 12V-2x6 cable is fully inserted

Intel also specifically notes that:

The graphics-card side must implement the basic logic for this signal
The graphics-card side should pull it down to ground through 4.7 kOhm
Monitoring this signal on the power-supply side is optional

It is not used to determine the allowed power level. That role still belongs to SENSE0 / SENSE1.

7. How to think about the relationship between these three generations of connectors

From a PC-building and connector-recognition perspective, you can simplify them into three generations:

2x3: the old 6-pin, typically positioned at 75W
2x4: the old 8-pin, typically positioned at 150W, and backward-compatible with 2x3
12V-2x6: the new high-power connector, up to 600W

Going one step further:

2x3 / 2x4 still follow the traditional auxiliary power-connector model
12V-2x6 standardizes high-power delivery, insertion state, and sideband communication together
The point of 12V-2x6 is not just higher wattage, but also stricter insertion detection and clearer power-state encoding

Summary

From Intel’s ATX 3.0 design guide, PCIe auxiliary power connectors for graphics cards are already divided very clearly into three layers:

2x3 corresponds to 75W
2x4 corresponds to 150W
12V-2x6 is aimed at up to 600W

And the real difference between 12V-2x6 and the old 12VHPWR is not just the name or the appearance, but also:

Updated mechanical structure for the main power pins and sideband pins
Revised SENSE0 / SENSE1 encoding rules
The addition of the more conservative Open-Open = 0W state
More complete connection and power-state handling through CARD_PWR_STABLE and CARD_CBL_PRES#

If you are looking into high-power graphics cards, modular PSU cables, or simply trying to understand the relationship between 6-pin, 8-pin, and 12V-2x6, Intel’s official design guide already lays out the framework quite clearly.

Reference Links

Intel EDC: PCI-Express (PCIe*) Add-in Card Connectors (Recommended) https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1a/pci-express-pcie-add-in-card-connectors-recommended/
Intel EDC: PCIe* Add-in Card 12V-2x6 Auxiliary Power Connector Sideband Signals https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1a/pcie-add-in-card-12v-2x6-auxiliary-power-connector-sideband-signals/
Intel EDC: SENSE0 & SENSE1 (Required) https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1a/sense0-amp-sense1-required/
Intel EDC: CARD_PWR_STABLE (Optional) https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1a/card-pwr-stable-optional/
Intel EDC: CARD_CBL_PRES# (Optional in Power Supply) https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1a/card-cbl-pres-optional-in-power-supply/
Intel EDC: Sideband Signals DC Specifications (Required) https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1a/sideband-signals-dc-specifications-required/

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2. `PCIe 2x3`: the old 6-pin, defined here as `75W`

3. `PCIe 2x4`: 8-pin, `150W`, and backward-compatible with `2x3`

4. `12V-2x6`: the new high-power connector, up to `600W`

5. Why `12V-2x6` is not the same as the early `12VHPWR`

6. What do the four `12V-2x6` sideband signals do?

1. `SENSE0 / SENSE1`

2. `CARD_PWR_STABLE`

3. `CARD_CBL_PRES#`